1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of testing the same, and more particularly, to a semiconductor memory device capable of merging data pins and a method of testing the same.
2. Description of the Related Art
Semiconductor memory devices are tested after manufacturing the semiconductor memory devices, so as to find defects that may be generated while manufacturing the semiconductor memory device and so as to improve reliability of the semiconductor memory devices. Generally, a tester is used for performing a plurality of test procedures. The tester may be electrically connected to the semiconductor memory device through a plurality of data pins.
When the data pins of the semiconductor memory device are merged, a single tester can be connected to more semiconductor memory devices. That is, more semiconductor memory devices can be tested simultaneously. Therefore, less time is required for testing the semiconductor memory devices, the expanse of carrying out the test is reduced and productivity of the semiconductor memory device is improved.
Conventionally, where at least two of the data pins of the semiconductor memory device are merged for testing the semiconductor memory device, the two data pins are electrically connected at the exterior of the semiconductor package and a data output buffer inside the semiconductor package determines to which data pin data is output.
For example, if an ‘X8’ memory device having eight data pins is tested based on the conventional method of merging the data pins, a data pin DQ0 and a data pin DQ4 are merged, a data pin DQ1 and a data pin DQ5 are merged, a data pin DQ2 and a data pin DQ6 are merged, and a data pin DQ3 and a data pin DQ7 are merged. After merging the data pins, a data output buffer in the semiconductor package outputs one of either data outputting to the data pin DQ0 or data outputting to the data pin DQ4, one of either data outputting to the data pin DQ1 or data outputting to the data pin DQ5, one of either data outputting to the data pin DQ2 or data outputting to the data pin DQ6, and one of either data outputting to the data pin DQ3 or data outputting to the data pin DQ7, for testing the semiconductor memory device. Accordingly, the number of data pins to be connected to the tester is reduced according to the conventional method of merging the data pins.
FIG. 1 is a block diagram showing a prior art approach for merging data pins of the semiconductor memory device.
An X8 semiconductor memory device having 8 data pins is shown in FIG. 1 as an example. The X8 semiconductor memory device is only illustrated as having four D0 pins (DQ0, DQ1, DQ4, DQ5) and relevant portions thereof and the remaining portions are omitted for the sake of clarity.
Referring to FIG. 1, the conventional semiconductor memory device 100 includes a memory cell array 110, an input/output (I/O) MUX 120, an I/O sense amp (S/A) 130, a DBMUX 140, a data output buffer 150 and data output pins DQ0, DQ1, DQ4 and DQ5. The DBMUX 140 may not be included in the conventional semiconductor memory device depending on the type of semiconductor memory device.
The memory cell array 110 includes a plurality of cells for storing data D0, D1, D4 and D5.
The I/O MUX 120 and the I/O S/A 130 are used to transmit data from the memory cell array 110 and amplify the data.
The DBMUX 140 multiplexes data to output the multiplexed data to a target data output pin.
The data output buffer 150 buffers data and outputs the buffered data to data output pins DQ0, DQ1, DQ4 and DQ5.
In order to reduce the number of data pins, the data output pins DQ0 and DQ4 are electrically connected to each other at an outside of the semiconductor memory device. Further, the data output pins DQ1 and DQ5 are electrically connected to each other at the outside of the conventional semiconductor memory device. When a test is performed on the conventional semiconductor memory device, the tester is electrically connected to one of data output pins DQ0 and DQ4 instead of both of data output pins DQ0 and DQ4. Further, the tester is connected to one of data output pins DQ1 and DQ5 instead of both of data output pins DQ1 and DQ5.
The data output buffer 150 outputs data D0 to the data output pin DQ0 and outputs data D1 to the data output pin DQ1 when a control signal RDM0 is activated. In this circumstance, the control signal RDM1 is inactivated to control the data output buffer 150 so as not to output data D4 to the data output pin DQ4 and so as not to output data D5 to the data output pin DQ5. Accordingly, the data D0 is output to the data output pin DQ0, and the data D1 is output to the data output pin DQ1. Since the data output pin DQ0 is electrically connected to the data output pin DQ4, the data D0 may be also output to the data output pin DQ4. Further, since the data output pin DQ1 is electrically connected to the data output pin DQ5, the data D1 may be also output to the data output pin DQ5.
The data output buffer 150 outputs data D4 to the data output pin DQ4 and outputs data D5 to the data output pin DQ5 when a control signal RDM1 is activated. In this circumstance, the control signal RDM0 is inactivated to control the data output buffer 150 so as not to output data D0 to the data output pin DQ0 and so as not to output data D1 to the data output pin DQ1. Accordingly, the data D4 is output to the data output pin DQ4, and the data D5 is output to the data output pin DQ5. Since the data output pin DQ4 is electrically connected to the data output pin DQ0, the data D4 may be also output to the data output pin DQ0. Since the data output pin DQ5 is electrically connected to the data output pin DQ1, the data D5 may be also output to the data output pin DQ1.
That is, if the tester is connected to one of two data output pins DQ0 and DQ4, the tester can read two data D0 and D4 according to the control signals RDM0 and RDM1. Further, if the tester is connected to one of two data output pins DQ1 and DQ5, the tester can read two data D1 and D5 according to the control signals RDM0 and RDM1.
As described above, the conventional semiconductor memory device in FIG. 1 can output two data bits to a single data output pin according to a control signal. Therefore, wiring between the tester and the conventional semiconductor memory device may be reduced.
FIG. 2 is a block diagram illustrating a method of testing a semiconductor memory device using a prior art approach for merging data pins.
An 8 X device is shown in FIG. 2 as an example of the semiconductor memory device.
Referring to FIG. 2, every two of data output pins DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6 and DQ7 of the semiconductor memory device are electrically connected. That is, the data output pin DQ0 is electrically connected to the data output pin DQ4, the data output pin DQ1 is electrically connected to the data output pin DQ5, the data output pin DQ2 is electrically connected to the data output pin DQ6, and the data output pin DQ3 is electrically connected to the data output pin DQ7.
The four pairs of data output pins are connected to the tester 210 without connecting the tester 210 to all of the data output pins of the semiconductor memory device. That is, the tester 210 is connected to a pair of the data output pins DQ0 and DQ4, a pair of the data output pins DQ1 and DQ5, a pair of the data output pins DQ2 and DQ6, and a pair of the data output pins DQ3 and DQ7. Accordingly, the tester 210 can be connected to more semiconductor memory devices to enable testing multiple semiconductor memory devices at once.
However, the conventional method of merging data pins of a semiconductor memory device causes a problem such that it is sometimes difficult to correlate operation characteristics of a semiconductor memory device in a test mode to operation characteristics of a semiconductor memory device in a normal mode. That is, it is difficult to ensure that the operation characteristics of the semiconductor memory device in the normal mode are fully reflected by the operation characteristics of the semiconductor memory device obtained from the test.
Since two data output pins are electrically connected at the outside of a package according to the conventional method of merging data pins, it is equivalent to the data output buffer providing a single buffered signal to two data pins. Accordingly, various I/O related parameters may be influenced during the test mode. For example, a load on the data pin may be increased during the test to affect the I/O related parameters. Therefore, a result of the test may show operation characteristics different from the operation characteristics of the semiconductor memory device in the normal mode. Such a problem becomes more serious in a high-speed memory device.